Multi-gate semiconductor devices, including and sometimes generally referred to as FinFET devices, have recently attracted more attention, because the devices offer higher performance per unit of power compared to similar, single gate/planar devices. With traditional metal oxide semiconductor (MOS) devices, as device geometries continue to shrink in an effort to increase performance of the device, short channel effects, such as off-state leakage current, increase. The leakage, in turn, increases idle power requirements for the device.
FinFET devices include a gate structure that can mitigate leakage current. The reduced leakage current not only reduces power consumption when the device is in an off state, but can also reduce a threshold voltage of the device, which can lead to increased switching speeds and reduced operating power consumption.
FinFET devices may desirably include germanium in the channel region of the device. Inclusion of germanium in a channel region can increase the mobility of charge carriers, which in turn, leads to increased device performance. Unfortunately, inclusion of germanium in the channel region has proven to be challenging to integrate into complimentary MOS (CMOS) devices. Various approaches for forming CMOS FinFET devices include the use of aspect ratio trapping to reduce a number of defects along a shallow trench isolation structure of the device. However, such processes generally require filling a narrow trench (e.g., less than 10 nm in width) with epitaxial material, which is difficult. In addition, buffer recess control in such devices can be less than desirable, resulting in channel height uniformity that is less than desirable. Accordingly, improved structures, devices, and methods of forming the structures and devices, which are relatively easy to fabricate with relatively uniform channel height are desired.